Search - test SDRAM

[Other resource] verilog SDRAM core

Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
Platform: | Size: 28424 | Author: 于飞 | Hits:

[Embeded-SCM Develop] S3C44B0X-test

Description: s3c44b0 的开发板测试的所有源代码及程序！！！汇编代码主要完成系统初始化，包括：禁止看门狗；禁止所有中断；初始化存储器（包括SDRAM）；设定锁相环倍频；使能所有单元模块时钟；初始化堆栈；设置中断等等 C语言代码主要是应用代码，包括：设置使用指令缓存；修改系统主时钟为32MHz； IO端口功能、方向设定；初始化中断；初始化DMF50081液晶模块；蜂鸣器测试；液晶显示测试； LED输出测试；定时器、PWM测试等；
Platform: | Size: 4392 | Author: 叶凌 | Hits:

[Other resource] sdram

Description: sdram test controller altera
Platform: | Size: 1520122 | Author: yangchun | Hits:

[OS Develop] SDRAM_test_code

Description: test sdram sample code
Platform: | Size: 6048 | Author: 鏋楀缓 | Hits:

[VHDL-FPGA-Verilog] verilog SDRAM core

Description: 我用过的verilog hdl写的SDRAM core源程序,经过测试应用-I used to write Verilog HDL source of SDRAM core, the test application
Platform: | Size: 27648 | Author: 于飞 | Hits:

[VHDL-FPGA-Verilog] SDRAMtest

Description: SDRAM的读写测试，便于大家深入了解SDRAM的工作原理！-SDRAM read and write tests for our in-depth understanding of the working principle of SDRAM!
Platform: | Size: 156672 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: sdram test controller altera -sdram test controller altera
Platform: | Size: 1519616 | Author: yangchun | Hits:

[DSP program] RD_DevuceID_Fr_McBSP0_to_SDRAM_ok

Description: dsp 5509a 存储器测试, SDRAM 测试程序,12Mx16=192/2=96Msdram 时钟-dsp 5509a memory test, SDRAM test procedure, 12Mx16 = 192/2 = 96Msdram clock
Platform: | Size: 434176 | Author: sam Hui | Hits:

[DSP program] test

Description: it is programed on dsk6455，and test * 1 Internal memory Version * 2 External memory(SDRAM) * 3 Flash * 4 Codec * 5 UserIO * 6 MemPattern(Fill pattern) * 7 MemPattern(Address Pattern) * 8 DSP * 9 LED/Swt * 10 Codec LoopBack *-it is programed on dsk6455, and test* 1 Internal memory Version* 2 External memory (SDRAM)* 3 Flash* 4 Codec* 5 UserIO* 6 MemPattern (Fill pattern)* 7 MemPattern (Address Pattern)* 8 DSP* 9 LED/Swt* 10 Codec LoopBack*
Platform: | Size: 251904 | Author: fan | Hits:

[OS Develop] test

Description: PXA27X裸机测试程序，包括FLASH、SDRAM、GPIO测试-PXA27x bare-metal test procedures, including FLASH, SDRAM, GPIO Test
Platform: | Size: 238592 | Author: Ronghua | Hits:

[VHDL-FPGA-Verilog] (fpga)sdram

Description: verilog 代码，读写SDRAM 不带仿真，需要自己编写测试文件-Verilog code, read and write SDRAM simulation without the need to prepare their own test documentation
Platform: | Size: 19935232 | Author: ch | Hits:

[ARM-PowerPC-ColdFire-MIPS] TEST

Description: S3c2440硬件测试程序，主要功能包括：SDRAM读写测试，整片Falsh读写测试，Flash擦除，坏块检测，flash复制数据到SDRAM-S3c2440 hardware testing procedures, the main features include: SDRAM read and write tests, reading and writing test Falsh whole, Flash erase bad block detection, flash copy the data to the SDRAM
Platform: | Size: 502784 | Author: 冯健 | Hits:

[VxWorks] ts201_Test_SDRAM

Description: DSP TS201 Test SDRAM Over
Platform: | Size: 613376 | Author: qin | Hits:

[ARM-PowerPC-ColdFire-MIPS] 2410test-code

Description: 三星2410试验源码,包括clock,nand ,sdram,led,key,timer-test-code of 2410,include clock,nand ,sdram,led,key,timer
Platform: | Size: 319488 | Author: dorisfu | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 程序说明: 本次实验控制开发板上面的SDRAM完成读写功能。先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。 part1是使用Modelsim仿真的工程 part2是在开发斑上面验证的工程目录说明: part1: part1_32是4m32SDRAM的仿真工程 part1_16是4m16SDRAM的仿真工程 \model文件夹里面是仿真模型 \rtl文件夹里面是源文件 \sim文件夹里面是仿真工程 \test_bench文件夹里面是测试文件 \wave文件夹里面是仿真波形 -Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform
Platform: | Size: 779264 | Author: 军军 | Hits:

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[Other resource] verilog SDRAM core

[Embeded-SCM Develop] S3C44B0X-test

[Other resource] sdram

[OS Develop] SDRAM_test_code

[VHDL-FPGA-Verilog] verilog SDRAM core

[VHDL-FPGA-Verilog] SDRAMtest

[VHDL-FPGA-Verilog] sdram

[DSP program] RD_DevuceID_Fr_McBSP0_to_SDRAM_ok

[DSP program] test

[OS Develop] test

[VHDL-FPGA-Verilog] (fpga)sdram

[ARM-PowerPC-ColdFire-MIPS] TEST

[VxWorks] ts201_Test_SDRAM

[ARM-PowerPC-ColdFire-MIPS] 2410test-code

[VHDL-FPGA-Verilog] sdram

[Other Embeded program] sdram

[DSP program] 3.2.3-sdram

[VHDL-FPGA-Verilog] SDRAM

[VHDL-FPGA-Verilog] SDRAM缓冲测试程序

[VHDL-FPGA-Verilog] FPGA读写SDRAM的实例

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